~ruther/verilog-riscv-semestral-project: testbench bc02aba5f50d84e93657a0601f713d990ecb8f11

~ruther/verilog-riscv-semestral-project

ref: bc02aba5f50d84e93657a0601f713d990ecb8f11 verilog-riscv-semestral-project/testbench d---------

773f4b99 — Rutherther 2 years ago

test: add simple cpu test

2929a779 — Rutherther 2 years ago

test: add basic testbenches