~ruther/verilog-riscv-semestral-project: testbench 773f4b9934627d8574aa6537bf7f289477336fe7

~ruther/verilog-riscv-semestral-project

ref: 773f4b9934627d8574aa6537bf7f289477336fe7 verilog-riscv-semestral-project/testbench d---------

773f4b99 — Rutherther 2 years ago

test: add simple cpu test

2929a779 — Rutherther 2 years ago

test: add basic testbenches