~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/testbench d--------- 
test: add ram test

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add simple cpu test

test: add basic testbenches
Do not follow this link