~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/testbench d---------
0a9a14b7 — Rutherther 3 years ago
test: add ram test
707b5bfc — Rutherther 3 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 3 years ago
feat: implement sb, sh, lb, lh support via masking
773f4b99 — Rutherther 3 years ago
test: add simple cpu test
2929a779 — Rutherther 3 years ago
test: add basic testbenches