~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/testbench d--------- 
test: add ram test

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add simple cpu test

test: add basic testbenches
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