~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/testbench d---------
0a9a14b7 — Rutherther 2 years ago
test: add ram test
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
773f4b99 — Rutherther 2 years ago
test: add simple cpu test
2929a779 — Rutherther 2 years ago
test: add basic testbenches