~ruther/verilog-riscv-semestral-project: src/ram.sv bb32d2ddcd68d2cf131760d9c1d99f9107c912f8

~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 498 bytes

ca9604e2 — Rutherther 1 year, 7 months ago

fix: offset ram by bytes, not bits

acf0f724 — Rutherther 1 year, 7 months ago

feat: implement sb, sh, lb, lh support via masking

8adc02d7 — Rutherther 1 year, 8 months ago

feat: add basic ram, alu, and register file