~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 498 bytes
bb32d2dd — Rutherther feat: add gcd program for testing 1 year, 7 months ago 
                                                                                
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import cpu_types::*;

module ram (
  input         clk, we,
  input [31:0]  a, wd,
  input         memory_mask_t mask,
  output [31:0] rd);

  reg [4095:0]    RAM;

  assign rd = RAM[(a[11:0] * 8) +:32]; // word aligned

  always @(posedge clk)
    if(we) begin
      case(mask)
        MEM_BYTE: RAM[(a[11:0] * 8) +:8] <= wd[7:0];
        MEM_HALFWORD: RAM[(a[11:0] * 8) +:16] <= wd[15:0];
        MEM_WORD: RAM[(a[11:0] * 8) +:32] <= wd[31:0];
        default: ;
      endcase
    end

endmodule
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