~ruther/verilog-riscv-semestral-project: .gitignore bb32d2ddcd68d2cf131760d9c1d99f9107c912f8

~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes

057ee98b — Rutherther 2 years ago

chore: add generated bin, obj gitignore files

65ab00a4 — Rutherther 2 years ago

chore: ignore obj_dir, vcd outputs

9c81ece2 — Rutherther 2 years ago

chore: add gitignore