~ruther/verilog-riscv-semestral-project

ref: b0f8702877121832dfdee7d921af417237673284 verilog-riscv-semestral-project/tests d---------
docs: add basic documentation
a079c57b — Rutherther 2 years ago
tests: add more custom tests
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
51842d38 — Rutherther 2 years ago
feat: add support for official tests
34b74f06 — Rutherther 2 years ago
tests: add python test environment for custom tests