~ruther/verilog-riscv-semestral-project

ref: aeab403896e168bc0c44a65883d46bb96689b7fb verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB 
feat: implement pipeline

tests: fix ram and control_unit tests to match newest architecture

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add basic testbenches
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