~ruther/verilog-riscv-semestral-project: testbench/tb_register_file.sv a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7

~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/testbench/tb_register_file.sv -rwxr-xr-x 837 bytes

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 2 years ago

test: add basic testbenches