~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
feat: store c results in memory addr 0
feat: add basic testing programs
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