~ruther/verilog-riscv-semestral-project

ref: a079c57bf9f1ab9cca6147599107bdd01e034121 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.5 KiB
feat: implement ebreak

Breaks the processor, can
exit the testcase
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
chore: add makefile for both verilog and c
feat: implement sb, sh, lb, lh support via masking
test: add simple cpu test
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