~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/tests/custom/custom_tests.py -rwxr-xr-x 1.9 KiB 
tests: add more custom tests

tests: add register dump, printing

feat: add support for official tests
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