~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB 
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
feat: implement pipeline

tests: fix ram and control_unit tests to match newest architecture

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add basic testbenches
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