~ruther/verilog-riscv-semestral-project

ref: 89e944c05b3c054fee5be670cd1b00e0e487819b verilog-riscv-semestral-project/programs/ma.c -rw-r--r-- 282 bytes
e5d2c0c5 — Rutherther 2 years ago 
tests: add simple ma.c program for testing misaligned access