~ruther/verilog-riscv-semestral-project

ref: 89e944c05b3c054fee5be670cd1b00e0e487819b verilog-riscv-semestral-project/programs/ma.c -rw-r--r-- 282 bytes
89e944c0 — Rutherther fix: sign extend only when misaligned access 2 years ago 
                                                                                
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int main() {

    // 0x0F000000
    __asm__(" \
      addi x1, x0, 0x0F\n \
      sll x1, x1, 24\n    \
      addi x1, x1, 0x0A\n \
      sw x1, 1(x0)\n      \
      lw x2, 1(x0)\n      \
      nop\n               \
      nop\n               \
      ebreak\n            \
    ");
}