~ruther/verilog-riscv-semestral-project: tests/custom 7d544e62c57a7e944d1572d147f7b271333a75aa

~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/tests/custom d---------

308a1462 — Rutherther 1 year, 6 months ago

tests: add register dump, printing

51842d38 — Rutherther 1 year, 6 months ago

feat: add support for official tests