~ruther/verilog-riscv-semestral-project

ref: 308a146292087449ecb82e4b7935f789ab21c64b verilog-riscv-semestral-project/tests/custom d---------
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
51842d38 — Rutherther 2 years ago
feat: add support for official tests