~ruther/verilog-riscv-semestral-project: src/instruction_decoder.sv 7ad5176683d16ac95ec356d2fe57bc9c753d698b

~ruther/verilog-riscv-semestral-project

ref: 7ad5176683d16ac95ec356d2fe57bc9c753d698b verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.7 KiB

27fcb8d9 — Rutherther 2 years ago

fix: do not use immediate in alu src for SB

32ebeea6 — Rutherther 2 years ago

feat(decoder): implement memory mask, conditional jumps

e3c95ad3 — Rutherther 2 years ago

feat: add instruction decoder