~ruther/verilog-riscv-semestral-project: src/ram.sv 773f4b9934627d8574aa6537bf7f289477336fe7

~ruther/verilog-riscv-semestral-project

ref: 773f4b9934627d8574aa6537bf7f289477336fe7 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 1 year, 8 months ago

feat: add basic ram, alu, and register file