~ruther/verilog-riscv-semestral-project

ref: 7581533cf757a3434d732348b90205ff6be3b404 verilog-riscv-semestral-project/testbench/tb_cpu_program.sv -rwxr-xr-x 1.9 KiB
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
51842d38 — Rutherther 2 years ago
feat: add support for official tests
32388b78 — Rutherther 2 years ago
feat: add support for loading and saving ram from disk
ee0204c8 — Rutherther 2 years ago
feat: pass program to execute by parameter
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
e7b5d989 — Rutherther 2 years ago
test: add cpu testbenches for c programs