~ruther/verilog-riscv-semestral-project

ref: 7581533cf757a3434d732348b90205ff6be3b404 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
89310129 — Rutherther 2 years ago
feat: implement pipeline
db85fb35 — Rutherther 2 years ago
tests: fix ram and control_unit tests to match newest architecture
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
2929a779 — Rutherther 2 years ago
test: add basic testbenches