~ruther/verilog-riscv-semestral-project

ref: 7581533cf757a3434d732348b90205ff6be3b404 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes
1d7c9233 — Rutherther 2 years ago 
chore: add python cache to gitignore
34b74f06 — Rutherther 2 years ago 
tests: add python test environment for custom tests
057ee98b — Rutherther 2 years ago 
chore: add generated bin, obj gitignore files
65ab00a4 — Rutherther 2 years ago 
chore: ignore obj_dir, vcd outputs
9c81ece2 — Rutherther 2 years ago 
chore: add gitignore