~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes
chore: add python cache to gitignore
tests: add python test environment for custom tests
chore: add generated bin, obj gitignore files
chore: ignore obj_dir, vcd outputs
chore: add gitignore
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