~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/tests/run.py -rwxr-xr-x 5.0 KiB 
tests: compile only once, copy proram, memory files to correct locations

feat: add support for official tests

tests: add python test environment for custom tests
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