~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/tests/run.py -rwxr-xr-x 5.0 KiB
18eeb2c5 — Rutherther 2 years ago 
tests: compile only once, copy proram, memory files to correct locations
51842d38 — Rutherther 2 years ago 
feat: add support for official tests
34b74f06 — Rutherther 2 years ago 
tests: add python test environment for custom tests