~ruther/verilog-riscv-semestral-project: tests/official/Makefile 740085c87e5cdab5e4d96e696df87f4a30e6f09f

~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/tests/official/Makefile -rwxr-xr-x 618 bytes

18eeb2c5 — Rutherther 1 year, 8 months ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 1 year, 8 months ago

feat: add support for official tests