~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/tests/official/official_tests.py -rwxr-xr-x 1.4 KiB 
tests: add register dump, printing

feat: add support for official tests
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