~ruther/verilog-riscv-semestral-project: tests/official/Makefile 73cf8a16605792f3455e04745c5e0007e1f08be5

~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/tests/official/Makefile -rwxr-xr-x 618 bytes

18eeb2c5 — Rutherther 2 years ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 2 years ago

feat: add support for official tests