~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv 732301c9f816051cb1b7937d011d3b21d10f68c2

~ruther/verilog-riscv-semestral-project

ref: 732301c9f816051cb1b7937d011d3b21d10f68c2 verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

707b5bfc — Rutherther 1 year, 8 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 8 months ago

test: add basic testbenches