~ruther/verilog-riscv-semestral-project

ref: 6da6eb9e4ee2ac5f96d5bed40c4c46d57a64c79f verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 1.8 KiB
89310129 — Rutherther 2 years ago 
feat: implement pipeline
acf0f724 — Rutherther 2 years ago 
feat: implement sb, sh, lb, lh support via masking
b7fa590c — Rutherther 2 years ago 
chore: add cpu types for various sources

Better orientation by name instead of
number