~ruther/verilog-riscv-semestral-project: testbench/tb_cpu_simple.sv 6ce1c83859b56b514f0a4536ddb388cacc77773e

~ruther/verilog-riscv-semestral-project

ref: 6ce1c83859b56b514f0a4536ddb388cacc77773e verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.4 KiB

707b5bfc — Rutherther 1 year, 7 months ago

chore: add makefile for both verilog and c

acf0f724 — Rutherther 1 year, 7 months ago

feat: implement sb, sh, lb, lh support via masking

773f4b99 — Rutherther 1 year, 7 months ago

test: add simple cpu test