~ruther/verilog-riscv-semestral-project

ref: 681756b70c4accd8c4caec6e97d8275a6359e5f9 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB
89310129 — Rutherther 2 years ago 
feat: implement pipeline
db85fb35 — Rutherther 2 years ago 
tests: fix ram and control_unit tests to match newest architecture
707b5bfc — Rutherther 2 years ago 
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago 
feat: implement sb, sh, lb, lh support via masking
2929a779 — Rutherther 2 years ago 
test: add basic testbenches