~ruther/verilog-riscv-semestral-project: testbench 66fd5da9a15539865c07f3516a5e396674a2bf16

~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/testbench d---------

773f4b99 — Rutherther 2 years ago

test: add simple cpu test

2929a779 — Rutherther 2 years ago

test: add basic testbenches