~ruther/verilog-riscv-semestral-project

ref: 66d141635b81de276634d3d9f97fe46c0ffb2f32 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 1.9 KiB
66d14163 — Rutherther 2 years ago
feat: move jumping to execute stage
f8e4e3ed — Rutherther 2 years ago
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
89310129 — Rutherther 2 years ago
feat: implement pipeline
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
b7fa590c — Rutherther 2 years ago
chore: add cpu types for various sources

Better orientation by name instead of
number