~ruther/verilog-riscv-semestral-project

ref: 5fe030988a21d47dd13af35a9b8697b2181cb6b7 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.5 KiB 
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add simple cpu test
Do not follow this link