~ruther/verilog-riscv-semestral-project

ref: 51842d387ac593fdcad90d2ed22e258a1c6780ee verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 96 bytes
34b74f06 — Rutherther 2 years ago 
tests: add python test environment for custom tests
057ee98b — Rutherther 2 years ago 
chore: add generated bin, obj gitignore files
65ab00a4 — Rutherther 2 years ago 
chore: ignore obj_dir, vcd outputs
9c81ece2 — Rutherther 2 years ago 
chore: add gitignore