~ruther/verilog-riscv-semestral-project (51842d387ac593fdcad90d2ed22e258a1c6780ee): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 51842d387ac593fdcad90d2ed22e258a1c6780ee verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 96 bytes

51842d38 — Rutherther feat: add support for official tests 1 year, 5 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat