~ruther/verilog-riscv-semestral-project

ref: 489df84930a405a04e27485ed89e224ec6fab8b1 verilog-riscv-semestral-project/tests/official d---------
308a1462 — Rutherther 3 years ago
tests: add register dump, printing
18eeb2c5 — Rutherther 3 years ago
tests: compile only once, copy proram, memory files to correct locations
51842d38 — Rutherther 3 years ago
feat: add support for official tests