~ruther/verilog-riscv-semestral-project: tests/official 38e84297e0e6abf0ec14d91878d5210792b801bd

~ruther/verilog-riscv-semestral-project

ref: 38e84297e0e6abf0ec14d91878d5210792b801bd verilog-riscv-semestral-project/tests/official d---------

18eeb2c5 — Rutherther 1 year, 5 months ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 1 year, 5 months ago

feat: add support for official tests