~ruther/verilog-riscv-semestral-project: testbench/tb_cpu_simple.sv 30a7f9492e5e15f2d64dded11bc5080af6b54ec5

~ruther/verilog-riscv-semestral-project

ref: 30a7f9492e5e15f2d64dded11bc5080af6b54ec5 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.4 KiB

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

773f4b99 — Rutherther 2 years ago

test: add simple cpu test