~ruther/verilog-riscv-semestral-project: testbench/tb_control_unit.sv 30a7f9492e5e15f2d64dded11bc5080af6b54ec5

~ruther/verilog-riscv-semestral-project

ref: 30a7f9492e5e15f2d64dded11bc5080af6b54ec5 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB

707b5bfc — Rutherther 1 year, 7 months ago

chore: add makefile for both verilog and c

acf0f724 — Rutherther 1 year, 7 months ago

feat: implement sb, sh, lb, lh support via masking

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches