~ruther/verilog-riscv-semestral-project: src/ram.sv 2929a779a9d6e451c15f91ac7124f4081e2a04b4

~ruther/verilog-riscv-semestral-project

ref: 2929a779a9d6e451c15f91ac7124f4081e2a04b4 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 1 year, 9 months ago

feat: add basic ram, alu, and register file