~ruther/verilog-riscv-semestral-project

ref: 2867e24626f7c4643ffa93cb6ea28f24d3eb2dae verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 2.7 KiB 
fix: force alu operation to addition for storing memory and pc

fix: propagate conditional jump from control_unit

feat: add control_unit wrapper over instruction_decoder
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