~ruther/verilog-riscv-semestral-project: src/cpu_types.sv 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8

~ruther/verilog-riscv-semestral-project

ref: 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

b7fa590c — Rutherther 2 years ago

chore: add cpu types for various sources

Better orientation by name instead of
number