~ruther/verilog-riscv-semestral-project: src/control_unit.sv 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8

~ruther/verilog-riscv-semestral-project

ref: 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 2.5 KiB

e44bfc9e — Rutherther 2 years ago

fix: propagate conditional jump from control_unit

52b05e5d — Rutherther 2 years ago

feat: add control_unit wrapper over instruction_decoder