~ruther/verilog-riscv-semestral-project: .gitignore 24eccbe0e5c0dabfc068a993b5167510756a4e22

~ruther/verilog-riscv-semestral-project

ref: 24eccbe0e5c0dabfc068a993b5167510756a4e22 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes

9c81ece2 — Rutherther 2 years ago

chore: add gitignore