~ruther/verilog-riscv-semestral-project

ref: 24eccbe0e5c0dabfc068a993b5167510756a4e22 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes
24eccbe0 — Rutherther refactor: parametrize register file 2 years ago 
                                                                                
1
2
3
4
5
6

.DS_Store
.idea
*.log
tmp/

.direnv/