~ruther/verilog-riscv-semestral-project (1d7c9233527974f1bfd8db7e0027d5871911b997): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

1d7c9233 — Rutherther chore: add python cache to gitignore 1 year, 5 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/