~ruther/verilog-riscv-semestral-project

ref: 181e94c4c368df49b63ee435f623436482f2f6a2 verilog-riscv-semestral-project/src/file_program_memory.sv -rwxr-xr-x 328 bytes
refactor: change program mem to file prog mem
feat: add program memory
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